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1 ? fn8124.0 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-352-6832 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x4c105 4k, novram/eeprom cpu supervisor with novram and output ports features ? 4kbit serial eeprom ?400khz serial interface speed ?16-byte page write mode ? one nibble novram ?120ns novram access speed ?autostore ?direct/bus access of novram bits ? four output ports ? operates at 3.3v 10% ? low voltage reset when v cc < 3v ?3% accurate thresholds available ?output signal shows low voltage condition ?activates novram autostore ?internal block on eeprom operation ? max eeprom/novram nonvo latile write cycle: 5ms ? high reliability ?1,000,000 endurance cycles ?guaranteed data retention: 100 years ? 20-lead tssop package description the low voltage x4c105 co mbines several functions into one device. the first is a 2-wire, 4kbit serial eeprom memory with write protection. a write pro- tect (wp) pin provides har dware protection for the upper half of this memory against inadve rtent writes. a one nibble novram is provided and occupies a sin- gle location. this allows ac cess of 4-bits in a single 150ns cycle. this is useful for tracking system opera- tion or process status. th e novram memory is com- pletely isolated from the serial memory section. a low voltage detect ci rcuit activates a reset pin when v cc drops below 3v. this signal also blocks new read or write operations and initiates a novram autostore. the autostore operation is pow- ered by an external capacitor to ensure that the value in the novram is always ma intained in the event of a power failure. the four novram bits also appear on four separate output pins to allow continuous control of external cir- cuitry, such as asics. intersil eeproms are designed and tested for appli- cations requiring extended endurance. inherent data retention is greater than 100 years. block diagram command decode and control logic hv generation timing and control eeprom array x decoder y decoder data register write control logic wp scl sda s1 s2 d0 d1 d2 d3 ce oe we i/o buffers control logic and timing static ram memory eeprom memory v cc v ss reset voltage monitor power-on reset low voltage detect cap supply o0 o1 o2 o3 output buffers and latches 4kbits data sheet march 18, 2005
2 fn8124.0 march 18, 2005 package/pinouts pin names device description serial memory section the device contains a 4kbit eeprom memory array with an internal address counter that allows it to be read sequentially, through its entire address space after receiving only 1 full address. the serial interface includes a current address read that requires no input address, but allows reading of the entire array starting from the address plus one of the last read or write. the address counter is also used for the write operation where the user may enter up to a page of data (16 bytes) after supplying only 1 full address. a wp pin provides hardware write protection. the wp pin active (high) prevents writes to the top half of the memory. this section is a 4k-bit vers ion of an industry standard 24c04 device. novram section the x4c105 also contains a single nibble of novram, with parallel access. this memory is com- pletely isolated from the serial memory section. the novram is intended to connect to the system mem- ory bus and uses standard ce , oe , and we pins to control access. a novram (or nonvolatile ram) consists of an sram part and an eeprom part. the sram is saved to eeprom only when po wer fails and the eeprom is recalled to sram only on power-up. output ports the x4c105 has four output only ports. these are active whenever power is applied to the device. the state of the output pin reflects the value in the respec- tive sram bit. as such, these port pins provide a non- volatile state. the conditions on the pins are restored when power is re-applied to the device. this can be valuable as a dip switch replacement for controlling the conditions of an asic or other system logic. low voltage detection when the internal low voltage detect circuitry senses that v cc is low, several things happen: ? the reset pin goes active. ? the contents of the sram are automatically saved to the ?shadow? eeprom. ? internal circuitry switches to provide power for the autostore operation from the cap pin so the store operation can complete even in the event of a catastrophic power failure. to insure this, it is rec- ommended that a 47f capacitor be used on the cap pin. the capacitor is continuously charged dur- ing normal operation to provide the necessary charge to complete the store operation. other inter- nal circuits are turned off to minimize current con- sumption during the store operations. ? communication to the device is interrupted and any command is aborted. if a se rial nonvolatile store is in progress when power fails, the operation is com- pleted and is followed by a novram autostore cycle. pin description v ss ground sda serial data v cc power scl serial clock wp write protect s1, s2 device select inputs cap external autostore capacitor d0-d3 novram i/os reset low voltage detect output ce novram chip enable oe novram read signal we novram write signal o0-o3 novram outputs s1 o3 v cc sda scl cap wp s2 reset ce we oe d0 d3 d2 d1 v ss o2 o1 o0 3 2 4 1 18 19 17 20 7 6 8 5 14 15 13 16 9 10 12 11 20-lead tssop x4c105
3 fn8124.0 march 18, 2005 capacitor backup circuit the diagram in figure 1 shows a represent ation of the capacitor backup circuit. figure 1. serial interface serial interface conventions the device supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the mast er always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this fam- ily operate as slaves in all applications. serial clock and data data states on the sda line can change only during scl low. sda state cha nges during scl high are reserved for indicating start and stop conditions. see figure 2. figure 2. valid data changes on the sda bus start novram autostore to internal voltage supply high when v cc > v trip low when v cc 4 fn8124.0 march 18, 2005 serial start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device contin uously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. see figure 3. serial stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop conditi on is also used to place the device into the standby power mode after a read sequence. a stop condition ca n only be issued after the transmitting device has rel eased the bus. see figure 2. serial acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will rel ease the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 4. the device will respond with an acknowle dge after recognition of a start condition and if the correct device identifier and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for the slave address byte when the device identifier and/or select bits are incorrect or when the device is busy, such as during a nonvolatile write. in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generate d by the master, the device will continue to transmit da ta. the device will terminate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. figure 3. valid start and stop conditions figure 4. acknowledge response from receiver scl sda start stop scl from master data output from data output from receiver 8 1 9 start acknowledge x4c105
5 fn8124.0 march 18, 2005 serial write operations byte write for a write operation, the device requires the slave address byte and a word address byte. this gives the master access to any one of the words in the array. after receipt of the word address byte, the device responds with an acknowledge, and awaits the next eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. during this internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. the sda out- put is at high impedance. see figure 5. an attempted write to a pr otected block of memory will suppress the acknowledge bit and the operation will terminate. page write the device is capable of a page write operation. it is initiated in the same manner as the byte write opera- tion; but instead of terminating the write cycle after the first data byte is transfer red, the master can transmit an unlimited number of 8-bit bytes. after the receipt of each byte, the device will respond with an acknowl- edge, and the address is internally incremented by one. the page address remains constant. when the counter reaches the end of the page, it ?rolls over? and goes back to ?0? on the same page. this means that the master can write 16 bytes to the page starting at any location on that page. if the master begins writing at location 10, and loads 12 bytes, then the first 5 bytes are written to locations 10 through 15, and the last 7 bytes are written to locations 0 through 6. after- wards, the address counter would point to location 7 of the page that was just writte n. see figure 6. if the master supplies more than 16 bytes of data, then new data over-writes the previous data, one byte at a time. figure 5. byte write sequence figure 6. writing 12 bytes to a 16-byte page starting at location 10. s t a r t s t o p slave address byte address data a c k a c k a c k sda bus signals from the slave signals from the master 0 address address 10 5 bytes n-1 7 bytes address = 6 address pointer ends here addr = 7 x4c105
6 fn8124.0 march 18, 2005 the master terminates the data byte loading by issu- ing a stop condition, whic h causes the device to begin the nonvolatile write cycle. as with the byte write oper- ation, all inputs are disabled until completion of the internal write cycle. refer to figure 7 for the address, acknowledge, and data transfer sequence. stops and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ack is sent, then the device will reset itself without performing t he write. the contents of the array will not be affected. figure 7. page write operation s t a r t s t o p slave address byte address data (n) a c k a c k a c k sda bus signals from the slave signals from the master 0 data (1) a c k (1 < n < 16) x4c105
7 fn8124.0 march 18, 2005 acknowledge polling the disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. once the stop condition is issued to indi- cate the end of the master?s byte load operation, the device initiates the internal non volatile write cycle. acknowledge polling can be initiated immediately. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the device is still busy with the high voltage cycle then no ack will be returned. if the device has completed the write operation, an ack will be returned and the host can then proceed with the read or write operation. refer to the flow chart in figure 8. figure 8. acknowledge polling sequence serial read operations read operations are initiated in the same manner as write operations with th e exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the device contai ns an address counter that maintains the address of the last word read incre- mented by one. therefore, if the last read was to address n, the next read o peration would access data from address n+1. on power-up, the address of the address counter is undefined, requiring a read or write operation for initialization. upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. the mas- ter terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop conditi on. refer to figure 9 for the address, acknowledge, and data transfer sequence. it should be noted that the ninth clock cycle of the read operation is not a ?don?t care.? to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and th en issue a stop condition. random read a random read operation allows the master to access any memory location in the ar ray. prior to issuing the slave address byte with the r/w bit set to one, the master must first perform a ?dummy? write operation. the master issues the star t condition and the slave address byte, receives an acknowledge, then issues the word address byte. after acknowledging receipts of the word address byte, the master immediately issues another start conditi on and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit word. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. refer to figure 10 for the address, acknowledge, and data transfer sequence. ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes high voltage cycle complete. continue command sequence? issue stop no continue normal read or write command sequence proceed yes x4c105
8 fn8124.0 march 18, 2005 figure 9. current address read sequence figure 10. random address read sequence the device offers a similar operation, called ?set cur- rent address,? where the device ends the transmission and issues a stop instead of the second start, shown in figure 10. the device goes into standby mode after the stop and all bus activity will be ignored until a start is detected. this operation loads the new address into the address counter. the next current address read operation will then read from the newly loaded address. this operation could be useful if the master knows the next address it needs to read, but is not ready for the data. sequential read sequential reads can be initiated as either a current address read or random address read. the first data byte is transmitted as with the other modes; however, the master now responds wi th an acknowledge, indicat- ing it requires additional dat a. the device continues to output data for each acknow ledge received. the master terminates the read operation by not responding with an acknowledge and then issu ing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all page and column addresses, allowing the entire memory con- tents to be serially read during one operation. at the end of the address space the counter ?rolls over? to address 0000 h and the device continues to output data for each acknowledge received. refer to figure 11 for the acknowledge and data transfer sequence. serial device addressing slave address byte following a start condition, the master must output a slave address byte. this byte consists of several parts: ? a device type identifie r that is always ?1010?. ? two bits that provide the device select bits. ? one bit that becomes the msb of the address. ? one bit of the slave command byte is a r/w bit. the r/w bit of the slave address byte defines the opera- tion to be performed. when the r/w bit is a one, then a read operation is selected. a zero selects a write operation. refer to figure 12. s t a r t s t o p slave address data a c k sda bus signals from the slave signals from the master 1 0 slave address byte address a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master x4c105
9 fn8124.0 march 18, 2005 figure 11. sequential read sequence after loading the entire slave address byte from the sda bus, the device compares the device select bits with the status of the device select pins. upon a cor- rect compare, the device outputs an acknowledge on the sda line. slave byte word address the word address is either supplied by the master or obtained from an internal counter. the internal counter is undefined on a power-up condition. write protect operations the wp pin provides write protection. the wp pin pro- tects the upper half of the array. table 1. write protected areas s t o p a c k a c k a c k data (2) slave address data (n) a c k sda bus signals from the slave signals from the master 1 data (n-1) (n is any integer greater than 1) data (1) 1 0 1 0 s2 s1 a8 r/w wp pin serial memory write protection low writes possible to all locations high no writes to 100h-1ffh, writes possible to 000h to 0ffh x4c105
10 fn8124.0 march 18, 2005 absolute maximum ratings temperature under bias .................... -65c to +135c storage temperature ......................... -65c to +150c voltage on any pin with respect to ground .................................-1.0v to 7.0v dc output current ................................................ 5 ma lead temperature (soldering, 10 seconds)........ 300c comment stresses above those liste d under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those indicated in the operational sections of this specifi- cation) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc operating characteristics v cc = 3.0 to 3.6v at -40 c to +85 c unless otherwise specified. notes: (1) the device enters the active state after any start, and re mains active until: 9 clock cyc les later if the device selec t bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. (2) the device goes into standby: 200ns after any stop, exce pt those that initiate a high voltage write cycle; t wc after a stop that initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slave addre ss byte. (3) v il min. and v ih max. are for reference only and are not tested. symbol parameter min. max. unit test conditions i cc1 (1) active supply current serial read or serial write (does not include the nonvolatile store operation) 2.0 ma v il = v cc x 0.1, v ih = v cc x 0.9, f scl = 400khz, sda = read/write operation, ce , oe , we , d0-d3 = v ih ; o0-o3, reset = open cap is tied to v cc ; v cc > v trip i cc2 (1) average active supply current during serial non- volatile store operation 3.0 ma v il = v cc x 0.1, v ih = v cc x 0.9, scl, sda = v ih ; wp, s1, s2 = v il , ce , oe , we , d0-d3 = v ih ; o0-o3, reset = open cap is tied to v cc . test during the n.v. write cycle. i cc3 (1) active supply current volatile novram read 3.0 ma v il = v cc x 0.1, v ih = v cc x 0.9, scl, sda = v ih ; wp, s1, s2 = v il , we = v ih ; ce , oe = v il , d0-d3, o0-o3, reset = open cap is tied to v cc ; v cc > v trip i cc4 (1) active supply current volatile novram write 3.0 ma v il = v cc x 0.1, v ih = v cc x 0.9, scl, sda = v ih ; wp, s1, s2 =v il , oe = v ih ; ce , we = v il , d0-d3 = v il or v ih , o0-o3, reset = open cap is tied to v cc ; v cc > v trip i cc5 (1) average active supply current over novram store, or active current dur- ing recall 3.0 ma v il = v cc x 0.1, v ih = v cc x 0.9, scl, sda, v ih ; wp, s1, s2 = v il , we , ce , oe = v ih ; d0-d3, o0-o3, reset = open cap is tied to v cc, v cc < v trip for store; v cc > v trip for re- call i sb1 (1) standby current 50 av il = v cc x 0.1, v ih = v cc x 0.9, scl, sda, ce , we , oe , d0-d3, = v ih , wp = v il , o0-o3, reset = open; cap is tied to v cc i li input leakage current 10 av in = gnd to v cc i lo output leakage current 10 av sda = gnd to v cc; device is in standby (2) v il (3) input low voltage -0.5 v cc x 0.3 v v ih (3 input high voltage v cc x 0.7 v cc + 0.5 v v hys schmitt trigger input hysteresis .05 x v cc v v ol output low voltage 0.4 v i ol = 2.0ma, v cc = 3.3v v oh output high voltage v cc - 0.4 v i oh = -1ma, v cc = 3.3v x4c105
11 fn8124.0 march 18, 2005 capacitance t a = 25 c, f = 1.0 mhz, v cc = 3.0-3.6v note: (4) this parameter is periodically sampled and not 100% tested. serial nonvolatile write cycle timing note: (5) t wc is the time from a valid stop condition at the end of a writ e sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user , unless acknowledge polling is used. serial memory ac characteristics serial ac test conditions equivalent ac output load circuit for v cc = 3.0-3.6v symbol parameter max. unit test conditions c i/o (4) input/output capacitance (sda, d0-d3, o0-o3) 8 pf v i/o = 0v c in (4) input capacitance (scl, wp, ce , we , oe , s1, s2) 6 pf v in = 0v symbol parameter min. typ. (5) max. unit t wc (5) write cycle time 3 5 ms input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load sda 1533 ? 100pf 3.3v for v ol = 0.4v and i ol = 2ma x4c105
12 fn8124.0 march 18, 2005 serial ac specifications t a = -40 c to +85 c, v cc = +3.0v to +3.6v, un less otherwise specified. notes: (7) this parameter is periodically sampled and not 100% tested. (8) cb = total capacitance of one bus line in pf. serial timing diagrams bus timing symbol parameter 400khz option unit min. max. f scl scl clock frequency 0 400 khz t in pulse width of spikes to be suppressed by the input filter 0 50 ns t aa scl low to sda data out valid 0.1 0.9 s t buf time the bus must be free before a new transmission can start 1.3 s t low clock low time 1.3 s t high clock high time 0.6 s t su:sta start condition setup time 0.6 s t hd:sta start condition hold time 0.6 s t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 s t dh data output hold time 50 ns t r sda and scl rise time 20 +.1cb (8) 300 ns t f sda and scl fall time 20 +.1cb (8) 300 ns t su: s1, s2,wp s1, s2, and wp setup time 0.4 ms t hd: s1, s2,wp s1, s2, and wp hold time 0.4 ms cb capacitive load for each bus line 400 pf t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r x4c105
13 fn8124.0 march 18, 2005 s1, s2, and wp pin timing write cycle timing novram ac characteristics novram ac conditions of test novram equivalent a.c load circuits t hd: s1,s2,wp scl sda in s1, s2, and wp t su: s1,s2,wp clk 1 clk 9 slave address byte start scl sda t wc 8 th bit of last byte ack stop condition start condition input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 3.3v 30pf 1596 ? 3093 ? x4c105
14 fn8124.0 march 18, 2005 novram read cycle specifications table 2. novram read cycle limits note: (9) t lz and t olz min.; t soe and t hoe min; and t hz and t ohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured, with cl = 5pf, from the point when ce or oe return high (whichever occurs first) to the time when the outputs are no longer driven. novram read cycle symbol parameter v cc = 3.0v-3.6v -40c to +85c unit min. max. t rc read cycle time 120 ns t ce chip enable access time 50 ns t oe output enable access time 50 ns t oh output hold from ce or oe high 0 ns t wes write enable high setups time 25 ns t weh write enable high hold time 25 ns t lz (9) chip enable to output in low z 0 ns t olz (9) output enable to output in low z 0 ns t hz (9) chip disable to output in high z 0 50 ns t ohz (9) output disable to output in high z 0 50 ns t soe (9) oe setup prior to operation in 2-wire mode 100 ms t hoe (9) oe hold following operation in 2-wire mode 100 ms t ohz t hz t ce t oe t olz t lz oe ce we d0-d3 t wes t weh t oh t rc x4c105
15 fn8124.0 march 18, 2005 novram write cycle specifications novram write cycle limits v cc = 3.0v-3.6v, t a = -40c to +85c note: (10) t lz and t olz min.; t soe and t hoe min; and t hz and t ohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured, with cl = 5pf, from the point when ce or oe return high (whichever occurs first) to the time when the outputs are no longer driven. symbol parameter min. max. unit t wc write cycle time 120 ns t wc1 write cycle time 170 ns t oes output enable high setup time 50 ns t oeh output enable high hold time 50 ns t cw chip enable to end of write input 50 ns t ce write setup time 0 ns t ch write hold time 0 ns t wp write pulse width 50 ns t wp1 write pulse width 100 ns t wph write pulse high recovery time 50 ns t ds data setup to end of write 40 ns t dh data hold time 0 ns t ndo new data output 50 ns t soe (10) oe setup prior to operation in 2-wire mode 100 ms t hoe (10) oe hold following operation in 2-wire mode 100 ms t wz write enable to output in high-z 50 ns t ow output active from end of write 0 ns t chz (10) chip disable to output in high z 0 50 ns t ohz (10) output disable to output in high z 0 50 ns x4c105
16 fn8124.0 march 18, 2005 novram we controlled write cycle novram ce controlled write cycle t cw t oeh t dh t ce t wp t ds oe we d0-d3 ce t oes t ch t wc t wph (data i/o) o0-o3 (data out) previous valid data t ndo new valid data data valid t cw t dh t wp t ds oe we ce data valid t oeh t oes t ce t ch t wph t wc o0-o3 (data out) previous valid data t ndo new valid data d0-d3 (data in) x4c105
17 fn8124.0 march 18, 2005 low voltage detect/power cycle parameters low voltage detect and output pin recall symbols parameters min. typ. max. unit v trip reset trip voltage-blank 2.80 2.875 2.95 v t rpd v cc detect to reset active 500 ns t purst power-up reset time out delay (t purst option 1)-default 100 200 400 ms t f v cc fall time from v cc = 3v to v cc = 2.5v 100 s t r v cc rise time from v cc = 2.5v to v cc = 3v 100 s t ovt output pins valid after v cc exceeds v trip 200 ns v rvalid reset valid v cc 1v v cc v trip rst t purst t purst t r t f t rpd v rvalid o0-o3 data valid v cc (min) t ovt t ovt data valid x4c105
18 fn8124.0 march 18, 2005 packaging information note: all dimensions in inches (in parentheses in millimeters) 20-lead plastic, tssop, package type v see detail ?a? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 - 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) x4c105
19 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8124.0 march 18, 2005 ordering information part mark convention v cc limits blank = 3.3v 10%, v trip = 2.8?2.95v temperature range blank = commercial = 0c to +70c i = industrial = -40c to +85c package v20 = 20 lead tssop device x4c105 x x ?x 20-lead tssop yyww xxx blank = 3.3v 10%, 0 to +70c, v trip = 2.8-2.95v i = 3.3 10%, -40 to +85c, v trip = 2.8-2.95v x4c105 x4c105
x4c105 printer friendly version cpu supervisor with novram and output ports datasheets, related docs & simulations description key features parametric data related devices ordering information part no. design-in status temp. package msl price us $ x4c105v20 active comm 20 ld tssop 1 3.02 x4c105v20-3c7889 active comm 20 ld tssop 1 3.61 x4c105v20-3t1c7889 active comm 20 ld tssop t+r 1 3.61 x4c105v20i active ind 20 ld tssop 1 3.33 x4c105v20-3a inactive comm 20 ld tssop 1 3.61 X4C105V20-3AT1 inactive comm 20 ld tssop t+r 1 3.61 the price listed is the manufacturer's suggested retail price for quantities between 100 and 999 units. however, prices in today's market are fluid and may change without notice. msl = moisture sensitivity level - per ipc/jedec j-std-020 smd = standard microcircuit drawing description the low voltage x4c105 combines several functions into one device. the first is a 2-wire, 4kbit serial eeprom memory with write protection. a write protect (wp) pin provides hardware protection for the upper half of this memory against inadvertent writes. a one nibble novram is provided and occupies a single location. this allows access of 4-bits in a single 150ns cycle. this is useful for tracking system operation or process status. the novram memory is completely isolated from the serial memory section. a low voltage detect circuit activates a reset pin when v cc drops below 3v. this signal also blocks new read or write operations and initiates a novram autostore. the autostore operation is powered by an external capacitor to ensure that the value in the novram is always maintained in the event of a power failure. the four novram bits also appear on four separate output pins to allow continuous control of external circuitry, such as asics. intersil eeproms are designed and tested for applications requiring extended endurance. inherent data retention is greater than 100 years. key f eatures 4kbit serial eeprom 400khz serial interface speed 16-byte page write mode one nibble novram 120ns novram access speed autostore direct/bus access of novram bits four output ports operates at 3.3v 10% low voltage reset when v cc < 3v 3% accurate thresholds available output signal shows low voltage condition activates novram autostore internal block on eeprom operation max eeprom/novram nonvolatile write cycle: 5ms high reliability 1,000,000 endurance cycles
guaranteed data retention: 100 years 20-lead tssop package related documentation application note(s): x4c105 novram features and applications datasheet(s): cpu supervisor with novram and output ports parametric data number of voltage monitors 1 v s range (v) 3.0 to 3.6 voltage threshold 1 2.875 (2.6%) reset output type active high watchdog timer (s) n manual reset n bus interface i 2 c eeprom size (kbits) 4 battery montor and switchover n fault detection register n suffix none por (ms) 200 rtc function n features novram related devices parametric table x4003 cpu supervisor x4005 cpu supervisor x4043 cpu supervisor with 4kbit eeprom x4045 cpu supervisor with 4kbit eeprom x4163 16k, 2k x 8 bit; cpu supervisor with 16k eeprom x4165 16k, 2k x 8 bit; cpu supervisor with 16k eeprom x4323 cpu supervisor with 32k eeprom x4325 cpu supervisor with 32k eeprom about us | careers | contact us | investors | legal | privacy | site map | subscribe | intranet ?2007. all rights reserved.

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